Although air gap design for interconnects in semiconductor devices having low-k (dielectric constant) and good RC time constant by replacing the interlayer silicon dioxide (dielectric constant k of about 4) with air (dielectric constant k of about 1), support is lacking on the via stack and metal line. This limits the number of metal layer interconnects that may be fabricated.
U.S. Pat. No. 5,559,055 to Chang et al. describes a method of decreasing the RC time constant by reducing the capacitance C by replacing the interlayer silicon dioxide (k=4) with air (k=1). Alternatively, the air space can also be filled with another low dielectric constant material in the range of about 2.2 to 3.4. In either case, the final effective dielectric constant of the device is lowered, thus lowering the RC time constant resulting in higher device speed.
U.S. Pat. No. 5,708,303 to Jeng describes a device and method of optimizing capacitance and performance for multilevel, damascene interconnects that may have air gaps between closely spaced metal interconnects. Crosstalk voltage is reduced by including a dielectric material having a higher permitivity between two metal layers to increase interlayer capacitance and inserting a low-dielectric constant material between metal lines.
U.S. Pat. No. 5,891,797 to Farrar describes a process of manufacturing integrated circuits for designing and implementing a hierarchical wiring system with the interconnection requirements sorted and designed into a particular wiring level according to length. Support structures, such as lateral ribs or intermediate posts fabricated of either insulating or conductive material, may be constructed to allow more flexibility in designing air bridge dimensions.
U.S. Pat. No. 5,882,963 to Kerber et al. describes a method of manufacturing a semiconductor component having capacitances occurring between contacts, interconnects, or metallizations reduced by filling cavities with air or gas. The cavities are produced between the semiconductor material and a passivation layer in a region wherein the interconnects are surrounded by dielectric and are subsequently closed by a further passivation layer.
U.S. Pat. No. 5,324,683 to Fitch et al. describes a method for forming an air region or an air bridge overlying a base layer to: provide for improved dielectric isolation of adjacent conductive layers; provide air-isolated conductive interconnects; and/or form many other microstructures or microdevices.
U.S. Pat. No. 5,548,099 to Cole, Jr. et al. describes a method for preserving an air bridge structure on an integrated circuit chip without sacrificing metallization routing area in an overlying high density interconnect structure. A protective layer is sublimed over the air bridge to provide mechanical strength while preventing contamination and deformation during processing.
U.S. Pat. No. 5,670,828 to Cheung et al. describes a semiconductor device with its control speed increased by forming air tunnels in the interwiring spaces of a conductive pattern to reduce intra-conductive layer capacitance.
U.S. Pat. No. 5,413,962 to Lur et al. describes a method of formation of a multilevel electrode metal structure and the interconnecting interlevel metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed, the interlevel dielectric material used in forming the structure is etched away leaving air dielectric between the levels.
U.S. Pat. No. 5,900,668 to Wollesen describes a semiconductor device having reduced parasitic capacitance, and thus increased integrated circuit speed, by removing sections of dielectric interlayers which do not support conductive patterns to form air gaps which may be filled in with a dielectric material having a low dielectric constant.